In the semiconductor processing art, practitioners always seek to achieve structures having a minimum size in order to save real estate. With respect to EEPROM, flash EPROM and EPROM cells, a critical limitation has been found to be a channel length between a drain region and a source region of the cell, the conductance of this channel being controlled by a floating gate. Ways have therefore been sought to decouple lithographic constraints from the channel length while at the same time retaining control over the critical channel length and producing a reliable device. In Applicants' copending Ser. No. 08/826,558 filed Apr. 4, 1997, the Applicants disclosed the formation of pyramidal-shaped holes, or truncated versions of same, in a semiconductor layer such that the sidewalls of the holes were disposed at a substantial angle to the face of the semiconductor layer. A tunnel dielectric layer was formed on the sidewalls and the hole then filled with a conductive floating gate. The semiconductor layer was previously implanted so that a source region was spaced away from the semiconductor face, and so that a drain region was disposed adjacent the face; a channel region of opposite conductivity type to the foregoing spaced apart the source and drain regions and was disposed adjacent at least one, and preferably all four, sidewalls. The partially vertical disposition of the channel region allowed its dimension to be decoupled from lithographic constrains. But further improvements can be made in array compactness.